Top critical review
Reviewed in the United States on November 12, 2018
Background on reader: Bachelor's in Software Engineering pursuing a Masters in Computer Engineering with 5 years experience in hardware/software integration. I found this textbook to be one of the worse textbooks I have owned. Teachers reading this review, Please use a different textbook for your classes. It's poorly organized. Descriptions of topics only scratch the surface, and the reader must go to the Appendices in order to delve into the topic. To be honest, I would have preferred a slightly longer chapter and have the author go into detail in the same chapter instead of creating a whole appendix. Chapter 2 section 3 barely talks about Pipelined Access and Multibanked Caches to Increase Bandwidth. I learned nothing from the section. Instead, Appendix B.3 covers what should have been in section 2.3. (Would it have been a problem to again provide the equations for the homework problems?) Sometimes the appendices listed are not even in the book. An example, in chapter 3 Instruction-Level Parallelism and Its Exploitation (section 3.2 to be exact), the author continually references an Appendix H. There is no Appendix H in the book. It only has Appendix A-C. The book is missing equations that are necessary for the homework problems (see Chapter 1 questions on MTTF, MTBF, MTTR, etc). Like I said, overall a very poorly written textbook. Anyone who is reading this, do yourself the favor, save your money, and buy a better book on Computer Architecture.